The present invention relates to a method for manufacturing a semiconductor elemental device wherein gate oxide films different in thickness are formed in a surface layer of a silicon substrate of a semiconductor wafer comprised of the silicon substrate or a silicon substrate of a semiconductor wafer of an SOI (Silicon On Insulator) structure or an SOS (Silicon On Sapphire) structure.
As a method for forming a semiconductor element or elemental device, a suitable manufacturing method is selected depending upon the transistor characteristic of a required MOSFET (MOS (Metal Oxide Semiconductor) Field Effect Transistor). For example, a method for, when a fast operating speed is required, thinning the thickness of a gate oxide film of a MOSFET and forming a short gate length is selected, and a method for, when a high voltage is applied, thickening the thickness of a gate oxide film and forming a long gate length in order to endure its electric field is selected.
As to the gate length, if a manufacturing method capable of forming the shortest gate length formed in a semiconductor wafer is selected, there is no problem in simultaneously forming a gate length longer than it along with it. However, complex manufacturing processes are required to form gate oxide films different in thickness on one semiconductor wafer.
FIG. 7 is an explanatory view showing a general manufacturing method of gate oxide films different in thickness.
In FIG. 7, reference numeral 1 indicates a semiconductor wafer, which is a semiconductor wafer constituted of one silicon substrate 2 comprised of silicon.
As shown in FIG. 7, device isolation regions 3, a first device forming region 4a and a second device forming region 4b (called “device forming regions 4” when it is not necessary to distinguish from each other) are set to the silicon substrate 2. The device forming regions 4 are formed with an nMOS (N channel MOS) and a pMOS (P channel MOS) each corresponding to a MOSFET. A field oxide film 5 is formed in the device isolation regions 3.
The field oxide film 5 is an insulating film made up of silicon dioxide, which is formed in the device isolation regions 3 of the silicon substrate 2 by a LOCOS (Local Oxidation Of Silicon) method or an STI (Shallow Trench Isolation) method. The field oxide film 5 electrically insulates and separates between the device forming regions 4 of the silicon substrate 2. The field oxide film 5 shown in FIG. 7 is formed by dry-oxidizing silicon of the device isolation regions 3 by the LOCOS method.
Reference numerals 6 indicate gate oxide films, which are insulating films comprised of silicon dioxide formed by oxidizing a surface layer of silicon of the silicon substrate 2 in the device forming regions 4 by a thermal oxidation method. A first gate oxide film (called a thin-film gate oxide film 6a) thin in thickness is formed in the first device forming region 4a, and a second gate oxide film (called a thick-film gate oxide film 6b) thick in thickness is formed in a second device forming region 4b. 
Reference numeral 10 indicates a resist mask, which is a mask member formed on the semiconductor wafer 1 by photolithography or the like. The resist mask 10 has the function of protecting regions masked upon an etching process and an ion implantation process or the like so as to be insensitive to etching and ion implantation.
The formation of gate oxide films different in thickness by a general manufacturing method will be described below in accordance with processes or process steps indicated by PZ using FIG. 7.
In PZ1, a silicon substrate 2 to which first and second device forming regions 4a and 4b and device isolation regions 3 are set, is prepared. A field oxide film 5 is formed in the device isolation regions 3 on the silicon substrate 2 by LOCOS to isolate and separate the first and second device forming regions 4a and 4b from each other respectively.
In PZ2, gate oxide films 6 of the same thickness are formed in the first and second device forming regions 4a and 4b by first thermal oxidation.
In PZ3, a resist mask 10, which covers the gate oxide film 6 in the second device forming region 4b for forming a thick-film gate oxide film 6b and the field oxide film 5 located therearound is formed by photolithography. With the resist mask 10 as a mask, the exposed gate oxide film 6 in the first device forming region 4a and the field oxide film 5 located therearound are removed by wet etching using hydrofluoric acid or the like. At this time, some of the field oxide film 5 around the first device forming region 4a is removed by etching.
In PZ4, the resist mask 10 is removed using a release agent such as acetone. Gate oxide films 6 are formed in the first and second device forming regions 4a and 4b respectively by second thermal oxidation. Thus, a thin-film gate oxide film 6a is newly formed in the first device forming region 4a from which the corresponding gate oxide film 6 is removed. The gate oxide film 6 corresponding to the second device forming region 4b is further thickened to form a thick-film gate oxide film 6b in the second device forming region 4b. 
Thereafter, a predetermined impurity for adjusting the threshold voltage of each MOSFET and its rated current is implanted in a manner similar to the normal manufacturing process, after which a gate electrode is formed to form a semiconductor elemental device by a general manufacturing method.
Thus, in the general manufacturing method, process steps for thermal oxidation and oxide film removal are repeated such that a desired thickness is reached where the gate oxide films 6 different in thickness are formed on one semiconductor wafer 1.
In order to attain simplification of the process steps for the general manufacturing method, there is a need to form the gate oxide films different in thickness on one semiconductor wafer by once-thermal oxidation.
In such a case, there is known one or a means wherein a region for forming a thick-film gate oxide film on a silicon substrate formed with a field oxide film and the field oxide film on both sides thereof are covered with a resist mask, ions of nitrogen (N) corresponding to one element (oxidation inhibiting element) for inhibiting a forming speed of an oxide film are implanted at an implantation energy of 25 keV and a dose of 5×1015/cm2, a region for forming a thin-film gate oxide film and the filed oxide film on both sides thereof are covered with a resist mask again after the removal of the above resist mask, ions of Argon (Ar) corresponding to one element (oxidation promoting element) for promoting a forming speed of an oxide film are implanted at an implantation energy of 58.8 keV and a dose of 5×1015/cm2, and thermal oxidation is done at 950° C. for one hour after the removal of the resist mask to form, by once-thermal oxidation, gate oxide films different in thickness, which are 60 angstroms and 390 angstroms in thickness (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 7 (1995)-94503 (paragraph 0044 in page 5-paragraph 0047 in page 7 and FIG. 4).
There is also known one or a means wherein well ions are implanted in a silicon substrate formed with a field oxide film, a region for forming a thin-film gate oxide film is covered with a resist mask, ions of Argon used as an oxidation promoting element are implanted at a dose of 1×1015/cm2 after the implantation of channel ions such that the peak of a concentration distribution is introduced so as to be brought to the neighborhood of the surface of the silicon substrate, and thermal oxidation is carried out after the resist mask is removed and channel ions are implanted into a region for forming a thin-film gate oxide film to thereby form, by once-thermal oxidation, gate oxide films different in thickness, which are 60 angstroms and 90 angstroms in thickness (refer to, for example, Japanese Unexamined Patent Publication No. Hei 10 (1998)-335656 (paragraph 0032 in page 6—paragraph 0037 in page 7, FIG. 1 and FIG. 2)).
In the general manufacturing method referred to above, however, the field oxide films 5 uncovered with the resist mask 10 are simultaneously etched and recessioned or etched back when the wet etching is done in the process step PZ3. Hence the region in the first device forming region 4a substantially expands and a parasitic transistor becomes apt to turn on, for example, whereby an influence on a thin-film transistor is apt to occur. This is particularly important to the semiconductor wafer 1 of the SOI structure or the SOS structure. Since the silicon substrate 2 for forming the semiconductor elemental device is thin in such a semiconductor wafer 1, it is difficult to make the field oxide film 5 thick sufficiently. The field oxide film 5 is etched back by wet etching in the process step PZ3, so that the field oxide film 5 at the edge of the first device forming region 4a becomes thin. Hence, a parasitic transistor low in threshold voltage is formed at the edge so that an off leak becomes apt to increase.
Since a control or management width of an etching rate is relatively large in the wet etching, the etching rate for each semiconductor wafer 1 varies so variations in etching amount are apt to occur, thereby increasing variations in the size of the first device forming region 4a. 
Such a problem is resolved by forming the gate oxide films different in thickness on one semiconductor wafer by once-thermal oxidation without repeating the process steps for the thermal oxidation and oxide-film removal. It is however necessary to consider the following upon implantation of the oxidation inhibiting element and the oxidation promoting element.
That is, since the implanted ions reach the surface of the silicon substrate and thereafter enter in a depth direction while their implantation energy is being lost, its concentration distribution results in a distribution configuration, i.e., a normal distribution in which as shown in FIG. 8, its concentration distribution is thin in the surface and the concentration thereof gradually increases in the depth direction and forms the peak, and thereafter the concentration decreases in the depth direction. In this case, an element for determining the distance (called diffusional intrusion length) from the surface of the silicon substrate to the peak of the concentration distribution is implantation energy. An element for determining the height of the peak of the concentration distribution is a dose.
FIG. 9 is a graph showing a diffusional intrusion length formed by implantation energy of Argon ions. It shows that the diffusional intrusion length becomes deep substantially in proportional to the implantation energy regardless of the dose.
On the surface side of the silicon substrate at the peak of the concentration distribution, the bonding of a silicon crystal is broken due to the intrusion of ions. Since the promoting action for the oxide film formation exists due to it, the forming speed of the oxide film becomes fast from the peak of the same Argon concentration as compared with the deep side.
The ion implantation has the above characteristics. Therefore, when, for example, Argon ions are used, the diffusional intrusion length becomes deep when their implantation energy is excessively increased, and the concentration of Argon in the neighborhood of the surface of the silicon substrate becomes thin, so the promoting action for oxide film formation by Argon falls and the forming speed of the oxide film becomes slow, thus resulting in the need for time upon the oxide film formation.
FIG. 10 shows the thickness of an oxide film formed by implanting Argon ions at a dose of 1×1014/cm2 while implantation energy of Argon ions is being changed, and thereafter performing thermal oxidation at 850° C. for 5 minutes.
In the same thermal oxidation condition as shown in FIG. 10, promoting action for oxide film formation increases until the implantation energy becomes 10 keV or so. However, the promoting action is saturated at 10 keV or so and is on the decline at 15 keV. That is, FIG. 10 shows that when the implantation energy is excessively made high, the formed oxide film becomes thin under the same thermal oxidation condition, and there is a need to prolong the time for thermal oxidation if an attempt is made to obtain the same oxide film.
Therefore, the technique of the patent document 1 is accompanied by problems that since ions of Argon used as the oxidation promoting element are implanted in high implantation energy like the implantation energy of 58.8 keV and the dose of 5×1015/cm2, the promoting action for the oxide film formation, of Argon in the neighborhood of the surface of the silicon substrate falls, and time is required upon formation of the oxide film if an attempt is made to obtain a predetermined film thickness.
Also, the technique is accompanied by problems that since Argon ions are implanted in high implantation energy, the diffusional intrusion length becomes deep to increase Argon ions that remain in the channel forming region, so the mobility of carriers (electrons or positive holes) in the channel forming region is reduced to thereby cause a reduction in rated current value of a transistor characteristic. Incidentally, since Argon is of an inert element, it does not exert an influence on the threshold voltage of the transistor characteristic.
The technique of the patent document 2 is accompanied by problems that since the depth of the peak is determined depending upon the implantation energy as described above because attention is focused only on the dose and ions of Argon used as the oxidation promoting element are implanted such that the peak of the concentration distribution is brought to the neighborhood of the surface of the silicon substrate, the concentration on the inner or deep side of the peak is diminished and the promoting action for oxide film formation by Argon is reduced, where the peak is excessively close to the surface, whereby time is required upon oxide film formation if an attempt is made to obtain a predetermined film thickness.
When the peak is excessively spaced away from the surface, a result similar to the patent document 1 is obtained.